/*
 * Copyright (c) 2002, 2025, Oracle and/or its affiliates. All rights reserved.
 * Copyright (c) 2012, 2025 SAP SE. All rights reserved.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 *
 * This code is free software; you can redistribute it and/or modify it
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 * published by the Free Software Foundation.
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 * This code is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * version 2 for more details (a copy is included in the LICENSE file that
 * accompanied this code).
 *
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 * 2 along with this work; if not, write to the Free Software Foundation,
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#ifndef CPU_PPC_VMREG_PPC_INLINE_HPP
#define CPU_PPC_VMREG_PPC_INLINE_HPP

#include "code/vmreg.hpp"
#include "register_ppc.hpp"

inline VMReg Register::as_VMReg() const {
  if (*this == noreg) return VMRegImpl::Bad();
  // Two halves, multiply by 2.
  return VMRegImpl::as_VMReg(encoding() << 1);
}

inline VMReg FloatRegister::as_VMReg() const {
  // Two halves, multiply by 2.
  return VMRegImpl::as_VMReg((encoding() << 1) + ConcreteRegisterImpl::max_gpr);
}

inline VMReg VectorRegister::as_VMReg() const {
  // Four halves, multiply by 4.
  return VMRegImpl::as_VMReg((encoding() << 2) + ConcreteRegisterImpl::max_fpr);
}

inline VMReg ConditionRegister::as_VMReg() const {
  return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_vr);
}

inline VMReg SpecialRegister::as_VMReg() const {
  return VMRegImpl::as_VMReg((encoding()) + ConcreteRegisterImpl::max_cnd);
}

#endif // CPU_PPC_VMREG_PPC_INLINE_HPP