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#ifndef CPU_RISCV_GLOBALDEFINITIONS_RISCV_HPP
#define CPU_RISCV_GLOBALDEFINITIONS_RISCV_HPP

const int StackAlignmentInBytes = 16;
const size_t pd_segfault_address = 1024;

// Indicates whether the C calling conventions require that
// 32-bit integer argument values are extended to 64 bits.
const bool CCallingConventionRequiresIntsAsLongs = false;

// RISCV has adopted a multicopy atomic model closely following
// that of ARMv8.
#define CPU_MULTI_COPY_ATOMIC

// To be safe, we deoptimize when we come across an access that needs
// patching. This is similar to what is done on aarch64.
#define DEOPTIMIZE_WHEN_PATCHING

#define SUPPORTS_NATIVE_CX8

#define SUPPORT_MONITOR_COUNT

#define SUPPORT_RESERVED_STACK_AREA

#define USE_POINTERS_TO_REGISTER_IMPL_ARRAY

// auipc useable for all cc -> cc calls and jumps
#define CODE_CACHE_SIZE_LIMIT ((2*G)-(2*K))

// The expected size in bytes of a cache line.
#define DEFAULT_CACHE_LINE_SIZE 64

// The default padding size for data structures to avoid false sharing.
#define DEFAULT_PADDING_SIZE DEFAULT_CACHE_LINE_SIZE

#endif // CPU_RISCV_GLOBALDEFINITIONS_RISCV_HPP